A method and circuit arrangement are known, such as described in commonly assigned U.S. Pat. No. 4,090,255, filed by H. H. Berger et al on Mar. 1, 1976, for operating an integrated semiconductor storage system whose storage cells include flip-flop circuits with bipolar transistors and Schottky diodes as read/write coupling elements. These cells use as load elements highly resistive resistors or transistors controlled as current sources, and whose write/read cycles are performed in several phases, and which are selected by voltage level changes to word lines and bit lines, and which for increasing the writing speed and the reading speed, and for decreasing the power dissipation, effect the discharge of the bit lines via the conductive memory cell transistors. The bit lines are discharged to ground via these conductive memory cell transistors. During the read phase of the memory, the bit lines are charged only slightly so that the charge current flowing through the memory cell is very low.
In recent years, there has been considerable activity in the development of logic circuits and of an integrated semiconductor memory technique with bipolar transistors. These developments have become known in the trade literature as merged transistor logic (MTL) or integrated injection logic (I.sup.2 L). Reference is made to articles published in IEEE Journal of Solid State Circuits, Vol. SC/7, No. 5, Oct. 1972, pages 340 to 346. Similar suggestions were also made in commonly assigned U.S. Pat. Nos. 3,736,477, filed Apr. 14, 1971, and 3,816,758, filed Mar. 15, 1973, by H. H. Berger and S. K. Wiedmann.
These concepts covering bipolar transistors are characterized by short switching times and are particularly suitable for designing extremely highly integrated memories and logic circuit arrays.
In commonly assigned U.S. Pat. No. 3,815,106, filed May 11, 1972, by S. K. Wiedmann, another memory is described which includes two logic circuits and where the collector of the inverting transistor of the one circuit is respectively coupled to the base of the inverting transistor of the other circuit. The two transistors are of inverse operation and form the actual flip-flop transistors. As a load element for both flip-flop transistors, a complementary transistor is connected via a specific line to each base circuit through which minority load carriers are injected, i.e. current is supplied. For addressing, i.e., for writing and reading of the memory cell, the base of each flip-flop transistor is additionally connected to the emitter of an associated additional complementary addressing transistor whose collector is applied to an associated bit line and whose base is applied to an address line.
Commonly assigned U.S. patent application Ser. No. 763,183, entitled "Highly Integrated Inverting Circuit" by S. K. Wiedmann, filed Jan. 27, 1977, now abandoned, discloses a highly integrated inverting logic circuit with a zone sequence forming an inverting transistor which is supplied with power by charge carrier injection via an injection region or injector close to the base-emitter junction and controlled on the base, which is characterized in that to the injection region a sensing circuit is connected via which the conductive state of the inverting transistor is sensed as a function of the current reinjected into the injection region when the transistor is conductive.
Memories with cells having a structure of the MTL type described in application Ser. No. 763,183 require for the selection of a cell the recharging of bit data and/or word line capacitances. The voltage swing of the bit lines corresponds approximately to the voltage swing of the selected word lines.
As mentioned hereinabove in connection with U.S. Pat. No. 4,090,255, the capacitive discharge currents are discharged to ground via the memory cells of the selected word line and via the word line driver. However, with a large number of memory cells in a matrix there is the disadvantage that the surface requirement of the driver circuits, the electric power dissipation for each driver, and the delay times in the selection of the word line are so excessive that the advantages normally obtained by the use of the MTL structure would be of little or no value.
Commonly assigned U.S. patent application Ser. No. 101,366, filed on Dec. 7, 1979 by S. K. Wiedmann, describes a method of controlling a semiconductor memory and a circuit arrangement which does not exhibit these disadvantages. This method is characterized in that in time before the selection for the storage matrix by a selection signal control logic, known per se, simultaneously applies control signals to a discharge circuit common to all memory cells, and to switching transistors which are then switched on, that, consequently, on the bit data and control lines the discharge currents of the line capacitances flow through the switching transistors, and jointly flow off via the discharge circuit. This circuit arrangement is characterized in that the bit lines within the memory matrix are connected to a discharge line which in turn is connected to a discharge circuit, and that the discharge circuit and all word and/or bit line switches are connected for their control via lines to control logic which is connected to the selection signal of the memory chip. Although with this discharge method, as well as with the circuit arrangement for carrying out that method, it is possible to use the minimum swing on the word line, to prevent capacitive peak currents on the voltage supply lines, and to have a relatively high integration, this solution has some disadvantages. The discharge operation and the selection operation of the bit lines have to take place successively. The rise of the sense current from the sensing circuit following the bit line selection decisively determines the access time of the storage cell. The bit and word line switching transistors operating in parallel all have to be switched on so that the restore time of the memory chip is extended by the time required for this step.